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Verilog - Vectors

·46 words
Study FPGA
icysamon
Author
icysamon
Electronics & Creator
Table of Contents

Circuit Diagram
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Code
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module top_module (
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0 ); // The module body begins after the module declaration 
    
    assign outv = vec;
    assign {o2, o1, o0} = vec; 
    
endmodule