↓ Skip to main content
icysamon’s blog

Verilog - for Loop

·85 words
Study FPGA
icysamon
Author
icysamon
Electronics & Creator
Table of Contents

Here, we’ll use reversing the order of 8 bits as an example.

for
# 

module top_module( 
    input [7:0] in,
    output [7:0] out
);

    always @(*) begin
        for (int i = 0; i < 8; i++)
            out[i] = in[8 - i - 1];
    end
    
endmodule

generate - for
# 

module top_module( 
    input [7:0] in,
    output [7:0] out
);

	generate
        genvar i;
        for (i = 0; i < 8; i = i + 1) begin: my_block_name
            assign out[i] = in[8 - i - 1];
        end
    endgenerate
    
endmodule